V360 Name
Class Name

Pretty Homework

Question 1

This is a sum of minterms.

I wrote a Karnaugh Map generator, but it only outputs expressions. First, I had to get all the minterm indices, which was easy enough when given the variable order.

And using these minterm expressions, we can translate them into minterm indices,
and see where to place the 1s on our Karnaugh Map!

Here are all the prime implicants.

We can then pick out 2 essential prime implicants from here – they’re both squares. We must also pick out a non-essential prime implicant to ensure the sum implies F. This, with a total of 3 terms in the sum, is the best possible solution. The other solution coming in second place here (with the (1, 9) and (3, 7) terms, seen above) would include one more term than is needed.

Here’s our most simple solution:

F(w, x, y, z) = w'x'z + xy + wy'

Question 2

We can represent this as a Karnaugh Map too! Let’s copy over the previous question’s work and fill it out for this.

Wow. Uh, that’s a pretty simple function. It’s just an inverted wx’y’z’

Question 3

I implemented it in Nandgame first, for the heck of it. Nandgame doesn’t have any nice way of representing vectors, so I end up choosing to represent the 32 outputs as two 16-bit numbers.

This is itself made up of smaller custom components:

The resulting tangle of wires translates to the resulting block diagram:

The 2→4 Decoder creates four signals that we later use as Enable signals for each 3→8 Decoder.

Question 4

Part 1

Alright, we should start small.

This looks like… it leaves n_{1</span> unchanged and XORs n0</span> to get the proper Gray code. Let’s try a slightly larger table.}

All the columns are XORed with their next column. …Let’s build this in Nandgame! It’s the most practical and appropriate software for this task! (Read: I’m too lazy to get a Verilog project up and running.)

And it works too! It’s actually ridiculously simple. It doesn’t even have much delay at all, beyond the cost of one XOR gate!

Part 2

module gray(output [3:0] o, input [3:0] i);
	xor (o[0], i[0], i[1]);
	xor (o[1], i[1], i[2]);
	xor (o[2], i[2], i[3]);
	buf (o[3], i[3]); // just to connect them
endmodule

And if I throw together a basic test bench:

module gray_tb;
	wire [3:0] ii; wire [3:0] oo;
	
	integer k = 0;
	assign {ii[3], ii[2], ii[1], ii[0] } = k;
	
	gray test(oo, ii);
	
	initial begin
		$dumpfile("gray_tb.vcd");
		$dumpvars(0, gray_tb);
		
		for (k = 0; k < 16; k = k + 1)
			#10 $display("done testing case %d", k);
		
		$finish;
	end
endmodule

Then we see this in GTKWave!